Shanghai electronic product development board development process

1. Functional design stage.

Designers of products applications, set some specifications such as function, speed, interface specifications, ambient temperature and power consumption, as the basis for future circuit design. Further planning software modules and hardware modules how to divide, which features should be integrated in the SOC, which features can be designed on the circuit board.

2. Design Description and Behavioral Verification After the energy supply design is completed, the SOC can be divided into several functional modules according to the functions and the IP cores that will be used to implement these functions are determined. This stage will affect the internal structure of the SOC and the interaction between the modules signal, and the reliability of future products. After determining the module, you can use VHDL or Verilog hardware description language to achieve the design of each module. Next, use circuit emulators of VHDL or Verilog to perform functional simulations of the design (behavioral simulation). Note that this functional simulation does not consider the actual delay of the circuit, but does not give accurate results.

3. Logic synthesis to determine the design description is correct, you can use the logic synthesis (synthesizer) for synthesis. In the process of synthesis, Shanghai Electronic Product Development needs to select the appropriate logic cell library as a reference for the synthesis of logic circuits. The programming style of the hardware language design description document is an important factor that determines the efficiency of the synthesis tool. In fact, the Syntax Syntax supports only a limited number of HDL grammars. Some syntax that is too abstract is only suitable for use as a simulation model for system evaluation, and can not be synthetically obtained by synthesis tools for gate-level netlist.

4. Gate Level Verification (Gate-Level Netlist Verification)

Gate-level functional verification is register-transfer-level verification. The main work is to confirm whether the integrated circuit meets the functional requirements, and the work is usually done by gate-level verification tools. Note that this stage simulation needs to consider the gate delay.

5. Layout and layout of the layout of the design of functional modules that will be properly arranged on the chip, planning their location. Cabling refers to the completion of the interconnection between the modules of the connection. Note that the connections between the modules are usually long, so the resulting delays can severely affect the performance of the SOC, especially at 0.25 micron process or more.